1. Technical Field
The present invention relates to a semiconductor memory device and a method of pre-charging I/O lines therein.
2. Description of Related Art
Current high-quality graphic systems require a memory that has sufficient capacity to implement high-resolution graphics and to perform 3D functions. These systems also require a larger bandwidth between the memory and a logic that performs a graphic engine function. To satisfy these requirements, Rambus DRAMs and Merged Memory and Logic (MML) have been introduced.
However, to realize a higher bandwidth in a DRAM core, such memory devices simultaneously operate a plurality of data buses differently than that of existing devices. Memory devices that have a large number of internal data buses and relatively few column addresses generally employ a structure in which column selecting lines are arranged in a region of a sense amplifier, and I/O lines are arranged over a cell array (see U.S. Pat. No. 5,892,719, entitled xe2x80x9cRedundancy Circuit Technique Applied Dram of Multi-bit I/O having Overlaid-DQ Busxe2x80x9d, issued on Apr. 6, 1999).
In memory devices having such a structure, a pre-charging operation is performed in a pre-charged state wherein all multiplexers are turned off to isolate local I/O lines and global I/O lines. When a column address strobe active command is input in the pre-charged state, corresponding local I/O lines and corresponding global I/O lines are connected to each other using a decoding address.
In such a method of controlling I/O lines, multiplexers are turned off so that local I/O lines and global I/O lines are respectively isolated during a pre-charging operation. Accordingly, to prevent a floating state of the respective I/O lines, each pair of I/O lines should have a pre-charging means associated therewith. However, in the case of a compound semiconductor memory device, the depth of the columns (i.e., a combination number by a column address) becomes lower, and the number of I/O lines becomes relatively larger. Accordingly, the number of pre-charging means set up in each line becomes larger.
Since such a pre-charging means is disposed on a memory core, the layout of the memory core becomes undesirably complex. In addition, as the number of the I/O lines increases, the size of the chip increases, as well as the low power consumption.
The problems stated above, as well as other related problems of the prior art, are solved by the present invention, a semiconductor memory device and a method for pre-charging I/O lines. The present invention allows for a simple layout of the memory core, a small chip size, and power consumption.
According to an aspect of the invention, there is provided a semiconductor memory device having first and second memory regions. The device includes a plurality of I/O sense amplifiers. A plurality of first and second local I/O line pairs are respectively arranged in parallel columns on the first and second memory regions. A plurality of first and second pre-charging means respectively pre-charge the plurality of first and second local I/O line pairs. A plurality of first and second switching means are arranged between the first and second memory regions and respectively connected to terminals of the plurality of first and second local I/O line pairs. A plurality of global I/O line pairs are arranged between the first and second memory regions and respectively connected to output terminals of the plurality of first and second switching means and the plurality of I/O sense amplifiers. Switching control means turns on all of the plurality of first and second switching means in a standby mode, turns off the plurality of second switching means in response to a read command or a write command corresponding to the first memory region, and simultaneously pre-charges the plurality of first and second local I/O line pairs and the plurality of global line pairs through the plurality of first and second pre-charging means by turning on any of the plurality of second switching means that have been turned off in response to a command subsequent to the read or the write command.
According to another aspect of the invention, the switching control means includes first combination means for controlling the plurality of first switching means in response to a row address strobe pre-charge command corresponding to the first memory region, a row address strobe pre-charge command corresponding to the second memory region, and a column address strobe active command corresponding to the second memory region. Second combination means control the plurality of second switching means in response to the row address strobe pre-charge command corresponding to the second memory region, the row address strobe pre-charge command corresponding to the first memory region, and a column address strobe active command corresponding to the first memory region.
According to yet another aspect of the invention the first combination means includes an inverter for inverting the row address strobe pre-charge command corresponding to the second memory region. A first NOR gate NOR-combines the row address strobe pre-charge command corresponding to the first memory region and an output of the inverter. A second NOR gate NOR-combines an output of the first NOR gate and the column address strobe active command corresponding to the second memory region. Buffer means buffer and provide an output of the second NOR gate to respective control terminals of the plurality of first switching means.
According to yet further another aspect of the present invention, the second combination means includes an inverter for inverting the row address strobe pre-charge command corresponding to the first memory region. A first NOR gate NOR-combines the row address strobe pre-charge command corresponding to the second memory region and an output of the inverter. A second NOR gate NOR-combines an output of the first NOR gate and the column address strobe active command corresponding to the first memory region. Buffer means buffer and provide an output of the second NOR gate to respective control terminals of the plurality of second switching means.
According to yet still further another aspect of the invention, the plurality of first and second local I/O line pairs are arranged in a same direction as a bit line and in a perpendicular direction with respect to a column selecting line and a word line.
According to an additional aspect of the invention, there is provided a method of pre-charging I/O lines of a semiconductor memory device that includes first and second memory regions. The method includes the step of respectively connecting first and second local I/O line pairs arranged on the first and second memory regions to global I/O line pairs in a standby mode, and simultaneously pre-charging the first and second local I/O line pairs and the global I/O line pairs by first and second pre-charging means respectively connected to the first and second I/O line pairs. The first local I/O line pairs are respectively disconnected from the global local I/O line pairs in response to a read command or a write command corresponding to the first memory region. The second local I/O line pairs are respectively re-connected with the global local I/O line pairs in response to a command subsequent to the read command or the write command, and the first and second local I/O line pairs and the global local I/O line pairs are simultaneously pre-charged by the first and second pre-charging means respectively connected to the first and second local I/O line pairs.
According to a yet additional aspect of the invention, there is provided a semiconductor memory device having upper memory banks and lower memory banks arranged in rows. The device includes a plurality of upper local I/O line pairs arranged in columns. A plurality of upper pre-charging means respectively pre-charge the plurality of upper local I/O line pairs. A plurality of lower local I/O line pairs are arranged in the columns. A plurality of lower pre-charging means respectively pre-charged the plurality of lower local I/O line pairs. A plurality of upper switching means are arranged between the upper and lower memory banks and respectively connected to terminals of the plurality of upper local I/O line pairs. A plurality of lower switching means are arranged between the upper and lower memory banks and respectively connected to terminals of the plurality of lower local I/O line pairs. A plurality of global I/O line pairs arranged between the upper and lower memory banks and respectively connected to outputs of the plurality of upper switching means and to outputs of the plurality of lower switching means. A plurality of I/O sense amplifiers are respectively connected to the plurality of global I/O line pairs. Switching control means turn off all of the plurality of upper switching means and the plurality of lower switching means in a standby mode, turn off the plurality of upper switching means or the plurality of lower switching means in response to a read command or a write command corresponding to the upper or the lower memory bank, and simultaneously pre-charge the plurality of upper I/O line pairs, the plurality of lower local I/O line pairs and the plurality of global I/O line pairs through the plurality of upper pre-charging means and the plurality of lower pre-charging means by turning on any of the switching means that have been turned off in response to a command subsequent to the read command or the write command.